1. Field of the Invention
The present invention concerns a charge pump circuit for implementing a voltage multiplier in integrated circuits operating with a relatively low supply voltage. The circuit is particularly suited for driving a high-side driver power device of a half-bridge output stage employing integrated DMOS transistors.
2. Discussion of the Related Art
Integration in the same chip of complex systems often composed of distinct circuit sections that are necessarily realized with structurally and functionally different devices, erasing and programming of read only memory cells, optimization of the driving conditions of integrated power devices in a half-bridge configuration, require or benefit from the availability of a biasing or driving voltage higher than the supply voltage of the integrated circuit. Often these requirements are satisfied by integrating special voltage multiplying circuits capable of producing, on an output ballast capacitance (storage capacitance) a voltage that is higher than the supply voltage (VCC). These circuits are commonly referred to as voltage multipliers or charge pump circuits.
A basic diagram of a charge pump circuit is depicted in FIG. 1.
Basically, the capacitor C2 stores electric charge that is fed thereto by transferring (pumping) the charge momentarily stored in a transfer capacitance C1 through a transfer diode D2. The intermittent charging of C1 through a diode D1 connected to VCC, and the discharging of the electric charge stored therein into the output capacitance C2, are controlled by a free-running local oscillator (OSC LDC)10. At steady state, the circuit operates as follows.
During an initial half cycle, the output of the local oscillator 10 is low and the capacitance C1 charges through the diode D1 to a voltage given by: VCC-Vd, where Vd represents the voltage drop across the charge diode D1. In the following half cycle, the output of the oscillator goes to a voltage VR, the node A assumes the voltage given by: VCC+VR-Vd, and the capacitance C1, discharges the electric charge that was stored therein during the preceding half cycle in the output storage capacitance C2. The capacitance C2, assumes the voltage VCP given by the following relation: EQU VCP=VCC+VR-2.Vd
It may be observed that for: VR=VCC, the circuit becomes substantially a voltage duplicator and provides an output voltage equal to twice the supply voltage less the voltage drop across the diodes.
Of course, the circuit may be composed of N basic circuit modules, in order to obtain an output voltage that is N-times the supply voltage less N-times the ohmic drop across a diode.
A practical embodiment of this type of circuit is depicted in FIG. 2. A regulated reference voltage VR is obtained, in the most simple case, by using a common voltage regulating stage composed of the transistor Q1, the resistor R1, the diode D3 and the Zener diode DZ1. By considering the voltage across the direct biased base-emitter junction of transistor Q1, given approximately by: Vbel=Vd3, where Vd3 is the voltage across the diode D3, the regulated voltage VR will be given by the following relations: ##EQU1## where VCC is the supply voltage, VZ is the Zener voltage and Vdrop is the sum of the junction voltage Vbel and of the voltage drop across the resistance R1 due to the current absorbed by the base of the regulating transistor Q1.
In a typical circuit as depicted in FIG. 2, Vdrop is about 1.2 V. However in a large number of applications, a relatively high current may be required and therefore the transistor Q1 is often replaced by a Darlington pair. In this last instance, Vdrop is about 2 V.
The voltage regulating stage provides a regulated supply to the local oscillator 10 and to the power stage that is made up of the two MOS transistors M1 and M2. The power stage has the function of driving the charge and discharge of the pump capacitance C1. When the load connected to an output (VCP) of a multiplied voltage source is relatively heavy and/or the transistors that are connected to the VCP line switch at a high frequency, relatively large capacitances are needed both for C1 (on the order of 10 nF) and for C2 (several hundreds of nF). As a consequence, the power stage (M1-M2) must be capable of delivering relatively large peaks of current (in the order of ten mA). The drawbacks of a conventional circuit configuration as the one described above are the following:
a) throughout the range of the supply voltage, the voltage drop across the transfer diodes D1 and D2 (equivalent to about 1.4 V) is "subtracted" from the output voltage VCP, as may be observed by considering the following relation: ##EQU2## b) For a relatively low supply voltage (e.g. VCC&lt;VZ+Vdrop), the voltage drop across the voltage regulator (Vdrop=2 V) subtracts from the available output voltage VCP, as may be observed from the following relation: PA1 c) The current driving the pump capacitance C1, which may have relatively large peaks is drawn from the regulated voltage line VR. This implies the need of properly designing the voltage regulator, to that is, employing large size components.
VCP=2*VCC-Vdrop-2Vd for VCC&lt;VZ+Vdrop; Both voltage drops contribute to limit the efficiency of the circuit when operating with a low supply voltage;